OF10 (frenetic.Frenetic.OpenFlow.OF10)

type 'a mask = 'a Frenetic_kernel__OpenFlow0x01.mask = {

m_value : 'a;

m_mask : 'a option;

}

val mask_of_sexp : (Ppx_sexp_conv_lib.Sexp.t ‑> 'a) ‑> Ppx_sexp_conv_lib.Sexp.t ‑> 'a mask

val sexp_of_mask : ('a ‑> Ppx_sexp_conv_lib.Sexp.t) ‑> 'a mask ‑> Ppx_sexp_conv_lib.Sexp.t

type switchId = int64

val switchId_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> switchId

val sexp_of_switchId : switchId ‑> Ppx_sexp_conv_lib.Sexp.t

type portId = Frenetic_kernel.Packet.int16

val portId_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> portId

val sexp_of_portId : portId ‑> Ppx_sexp_conv_lib.Sexp.t

type queueId = int32

val queueId_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> queueId

val sexp_of_queueId : queueId ‑> Ppx_sexp_conv_lib.Sexp.t

type xid = Frenetic_kernel.OpenFlow_Header.xid

type pattern = Frenetic_kernel__OpenFlow0x01.pattern = {

dlSrc : Frenetic_kernel.Packet.dlAddr option;

dlDst : Frenetic_kernel.Packet.dlAddr option;

dlTyp : Frenetic_kernel.Packet.dlTyp option;

dlVlan : Frenetic_kernel.Packet.dlVlan option;

dlVlanPcp : Frenetic_kernel.Packet.dlVlanPcp option;

nwSrc : Frenetic_kernel.Packet.nwAddr mask option;

nwDst : Frenetic_kernel.Packet.nwAddr mask option;

nwProto : Frenetic_kernel.Packet.nwProto option;

nwTos : Frenetic_kernel.Packet.nwTos option;

tpSrc : Frenetic_kernel.Packet.tpPort option;

tpDst : Frenetic_kernel.Packet.tpPort option;

inPort : portId option;

}

val pattern_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> pattern

val sexp_of_pattern : pattern ‑> Ppx_sexp_conv_lib.Sexp.t

type pseudoPort = Frenetic_kernel__OpenFlow0x01.pseudoPort =

| PhysicalPort of portId

| InPort

| Table

| Normal

| Flood

| AllPorts

| Controller of int

| Local

val pseudoPort_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> pseudoPort

val sexp_of_pseudoPort : pseudoPort ‑> Ppx_sexp_conv_lib.Sexp.t

type action = Frenetic_kernel__OpenFlow0x01.action =

| Output of pseudoPort

| SetDlVlan of Frenetic_kernel.Packet.dlVlan

| SetDlVlanPcp of Frenetic_kernel.Packet.dlVlanPcp

| SetDlSrc of Frenetic_kernel.Packet.dlAddr

| SetDlDst of Frenetic_kernel.Packet.dlAddr

| SetNwSrc of Frenetic_kernel.Packet.nwAddr

| SetNwDst of Frenetic_kernel.Packet.nwAddr

| SetNwTos of Frenetic_kernel.Packet.nwTos

| SetTpSrc of Frenetic_kernel.Packet.tpPort

| SetTpDst of Frenetic_kernel.Packet.tpPort

| Enqueue of pseudoPort * queueId

val action_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> action

val sexp_of_action : action ‑> Ppx_sexp_conv_lib.Sexp.t

type timeout = Frenetic_kernel__OpenFlow0x01.timeout =

| Permanent

| ExpiresAfter of Frenetic_kernel.Packet.int16

val timeout_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> timeout

val sexp_of_timeout : timeout ‑> Ppx_sexp_conv_lib.Sexp.t

type flowModCommand = Frenetic_kernel__OpenFlow0x01.flowModCommand =

| AddFlow

| ModFlow

| ModStrictFlow

| DeleteFlow

| DeleteStrictFlow

val flowModCommand_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> flowModCommand

val sexp_of_flowModCommand : flowModCommand ‑> Ppx_sexp_conv_lib.Sexp.t

type flowMod = Frenetic_kernel__OpenFlow0x01.flowMod = {

command : flowModCommand;

pattern : pattern;

priority : Frenetic_kernel.Packet.int16;

actions : action list;

cookie : int64;

idle_timeout : timeout;

hard_timeout : timeout;

notify_when_removed : bool;

apply_to_packet : int32 option;

out_port : pseudoPort option;

check_overlap : bool;

}

val flowMod_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> flowMod

val sexp_of_flowMod : flowMod ‑> Ppx_sexp_conv_lib.Sexp.t

type payload = Frenetic_kernel__OpenFlow0x01.payload =

| Buffered of int32 * Cstruct.t Core.sexp_opaque

| NotBuffered of Cstruct.t Core.sexp_opaque

val payload_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> payload

val sexp_of_payload : payload ‑> Ppx_sexp_conv_lib.Sexp.t

type packetInReason = Frenetic_kernel__OpenFlow0x01.packetInReason =

| NoMatch

| ExplicitSend

val packetInReason_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> packetInReason

val sexp_of_packetInReason : packetInReason ‑> Ppx_sexp_conv_lib.Sexp.t

type packetIn = Frenetic_kernel__OpenFlow0x01.packetIn = {

input_payload : payload;

total_len : Frenetic_kernel.Packet.int16;

port : portId;

reason : packetInReason;

}

val packetIn_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> packetIn

val sexp_of_packetIn : packetIn ‑> Ppx_sexp_conv_lib.Sexp.t

type flowRemovedReason = Frenetic_kernel__OpenFlow0x01.flowRemovedReason =

| IdleTimeout

| HardTimeout

| Delete

val flowRemovedReason_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> flowRemovedReason

val sexp_of_flowRemovedReason : flowRemovedReason ‑> Ppx_sexp_conv_lib.Sexp.t

type flowRemoved = Frenetic_kernel__OpenFlow0x01.flowRemoved = {

pattern : pattern;

cookie : int64;

priority : Frenetic_kernel.Packet.int16;

reason : flowRemovedReason;

duration_sec : int32;

duration_nsec : int32;

idle_timeout : timeout;

packet_count : int64;

byte_count : int64;

}

val flowRemoved_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> flowRemoved

val sexp_of_flowRemoved : flowRemoved ‑> Ppx_sexp_conv_lib.Sexp.t

type packetOut = Frenetic_kernel__OpenFlow0x01.packetOut = {

output_payload : payload;

port_id : portId option;

apply_actions : action list;

}

val packetOut_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> packetOut

val sexp_of_packetOut : packetOut ‑> Ppx_sexp_conv_lib.Sexp.t

type statsReq = Frenetic_kernel__OpenFlow0x01.statsReq = {

sr_of_match : pattern;

sr_table_id : Frenetic_kernel.Packet.int8;

sr_out_port : pseudoPort option;

}

val statsReq_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> statsReq

val sexp_of_statsReq : statsReq ‑> Ppx_sexp_conv_lib.Sexp.t

type request = Frenetic_kernel__OpenFlow0x01.request =

| DescriptionRequest

| FlowTableStatsRequest

| IndividualRequest of statsReq

| AggregateRequest of statsReq

| PortRequest of pseudoPort option

val request_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> request

val sexp_of_request : request ‑> Ppx_sexp_conv_lib.Sexp.t

type descriptionStats = Frenetic_kernel__OpenFlow0x01.descriptionStats = {

manufacturer : string;

hardware : string;

software : string;

serial_number : string;

datapath : string;

}

val descriptionStats_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> descriptionStats

val sexp_of_descriptionStats : descriptionStats ‑> Ppx_sexp_conv_lib.Sexp.t

type individualStats = Frenetic_kernel__OpenFlow0x01.individualStats = {

table_id : Frenetic_kernel.Packet.int8;

of_match : pattern;

duration_sec : int32;

duration_nsec : int32;

priority : Frenetic_kernel.Packet.int16;

idle_timeout : Frenetic_kernel.Packet.int16;

hard_timeout : Frenetic_kernel.Packet.int16;

cookie : int64;

packet_count : int64;

byte_count : int64;

actions : action list;

}

val individualStats_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> individualStats

val sexp_of_individualStats : individualStats ‑> Ppx_sexp_conv_lib.Sexp.t

type aggregateStats = Frenetic_kernel__OpenFlow0x01.aggregateStats = {

total_packet_count : int64;

total_byte_count : int64;

flow_count : int32;

}

val aggregateStats_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> aggregateStats

val sexp_of_aggregateStats : aggregateStats ‑> Ppx_sexp_conv_lib.Sexp.t

type portStats = Frenetic_kernel__OpenFlow0x01.portStats = {

port_no : Frenetic_kernel.Packet.int16;

rx_packets : int64;

tx_packets : int64;

rx_bytes : int64;

tx_bytes : int64;

rx_dropped : int64;

tx_dropped : int64;

rx_errors : int64;

tx_errors : int64;

rx_frame_err : int64;

rx_over_err : int64;

rx_crc_err : int64;

collisions : int64;

}

val portStats_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> portStats

val sexp_of_portStats : portStats ‑> Ppx_sexp_conv_lib.Sexp.t

type reply = Frenetic_kernel__OpenFlow0x01.reply =

| DescriptionRep of descriptionStats

| IndividualFlowRep of individualStats list

| AggregateFlowRep of aggregateStats

| PortRep of portStats list

val reply_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> reply

val sexp_of_reply : reply ‑> Ppx_sexp_conv_lib.Sexp.t

type wildcards = Frenetic_kernel__OpenFlow0x01.wildcards = {

in_port : bool;

dl_vlan : bool;

dl_src : bool;

dl_dst : bool;

dl_type : bool;

nw_proto : bool;

tp_src : bool;

tp_dst : bool;

nw_src : int;

nw_dst : int;

dl_vlan_pcp : bool;

nw_tos : bool;

}

val wildcards_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> wildcards

val sexp_of_wildcards : wildcards ‑> Ppx_sexp_conv_lib.Sexp.t

type portConfig = Frenetic_kernel__OpenFlow0x01.portConfig = {

down : bool;

no_stp : bool;

no_recv : bool;

no_recv_stp : bool;

no_flood : bool;

no_fwd : bool;

no_packet_in : bool;

}

val portConfig_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> portConfig

val sexp_of_portConfig : portConfig ‑> Ppx_sexp_conv_lib.Sexp.t

type stpState = Frenetic_kernel__OpenFlow0x01.stpState =

| Listen

| Learn

| Forward

| Block

val stpState_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> stpState

val sexp_of_stpState : stpState ‑> Ppx_sexp_conv_lib.Sexp.t

type portState = Frenetic_kernel__OpenFlow0x01.portState = {

down : bool;

stp_state : stpState;

}

val portState_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> portState

val sexp_of_portState : portState ‑> Ppx_sexp_conv_lib.Sexp.t

type portFeatures = Frenetic_kernel__OpenFlow0x01.portFeatures = {

f_10MBHD : bool;

f_10MBFD : bool;

f_100MBHD : bool;

f_100MBFD : bool;

f_1GBHD : bool;

f_1GBFD : bool;

f_10GBFD : bool;

copper : bool;

fiber : bool;

autoneg : bool;

pause : bool;

pause_asym : bool;

}

val portFeatures_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> portFeatures

val sexp_of_portFeatures : portFeatures ‑> Ppx_sexp_conv_lib.Sexp.t

type portDescription = Frenetic_kernel__OpenFlow0x01.portDescription = {

port_no : portId;

hw_addr : Frenetic_kernel.Packet.dlAddr;

name : string;

config : portConfig;

state : portState;

curr : portFeatures;

advertised : portFeatures;

supported : portFeatures;

peer : portFeatures;

}