Module Frenetic.OpenFlow0x04

type 'a mask = 'a Frenetic_kernel__OpenFlow0x04.mask = {
m_value : 'a;
m_mask : 'a option;
}
val mask_of_sexp : (Ppx_sexp_conv_lib.Sexp.t ‑> 'a) ‑> Ppx_sexp_conv_lib.Sexp.t ‑> 'a mask
val sexp_of_mask : ('a ‑> Ppx_sexp_conv_lib.Sexp.t) ‑> 'a mask ‑> Ppx_sexp_conv_lib.Sexp.t
type 'a asyncMask = 'a Frenetic_kernel__OpenFlow0x04.asyncMask = {
m_master : 'a;
m_slave : 'a;
}
val asyncMask_of_sexp : (Ppx_sexp_conv_lib.Sexp.t ‑> 'a) ‑> Ppx_sexp_conv_lib.Sexp.t ‑> 'a asyncMask
val sexp_of_asyncMask : ('a ‑> Ppx_sexp_conv_lib.Sexp.t) ‑> 'a asyncMask ‑> Ppx_sexp_conv_lib.Sexp.t
type payload = Frenetic_kernel__OpenFlow0x04.payload =
| Buffered of int32 * Cstruct.t
| NotBuffered of Cstruct.t
val payload_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> payload
val sexp_of_payload : payload ‑> Ppx_sexp_conv_lib.Sexp.t
type xid = Frenetic_kernel.OpenFlow_Header.xid
val xid_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> xid
val sexp_of_xid : xid ‑> Ppx_sexp_conv_lib.Sexp.t
type int12 = Frenetic_kernel.Packet.int16
val int12_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> int12
val sexp_of_int12 : int12 ‑> Ppx_sexp_conv_lib.Sexp.t
type int24 = int32
val int24_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> int24
val sexp_of_int24 : int24 ‑> Ppx_sexp_conv_lib.Sexp.t
type int128 = int64 * int64
val int128_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> int128
val sexp_of_int128 : int128 ‑> Ppx_sexp_conv_lib.Sexp.t
val val_to_mask : 'a1 ‑> 'a1 mask
val ip_to_mask : (Frenetic_kernel.Packet.nwAddr * int32) ‑> Frenetic_kernel.Packet.nwAddr mask
type switchId = int64
val switchId_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> switchId
val sexp_of_switchId : switchId ‑> Ppx_sexp_conv_lib.Sexp.t
type groupId = int32
val groupId_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> groupId
val sexp_of_groupId : groupId ‑> Ppx_sexp_conv_lib.Sexp.t
type portId = int32
val portId_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> portId
val sexp_of_portId : portId ‑> Ppx_sexp_conv_lib.Sexp.t
type tableId = Frenetic_kernel.Packet.int8
val tableId_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> tableId
val sexp_of_tableId : tableId ‑> Ppx_sexp_conv_lib.Sexp.t
type bufferId = int32
val bufferId_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> bufferId
val sexp_of_bufferId : bufferId ‑> Ppx_sexp_conv_lib.Sexp.t
type switchFlags = Frenetic_kernel__OpenFlow0x04.switchFlags = {
frag_normal : bool;
frag_drop : bool;
frag_reasm : bool;
}
val switchFlags_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> switchFlags
val sexp_of_switchFlags : switchFlags ‑> Ppx_sexp_conv_lib.Sexp.t
type switchConfig = Frenetic_kernel__OpenFlow0x04.switchConfig = {
flags : switchFlags;
miss_send_len : Frenetic_kernel.Packet.int16;
}
val switchConfig_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> switchConfig
val sexp_of_switchConfig : switchConfig ‑> Ppx_sexp_conv_lib.Sexp.t
type helloFailed = Frenetic_kernel__OpenFlow0x04.helloFailed =
| HelloIncompatible
| HelloPermError
val helloFailed_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> helloFailed
val sexp_of_helloFailed : helloFailed ‑> Ppx_sexp_conv_lib.Sexp.t
type badRequest = Frenetic_kernel__OpenFlow0x04.badRequest =
| ReqBadVersion
| ReqBadType
| ReqBadMultipart
| ReqBadExp
| ReqBadExpType
| ReqPermError
| ReqBadLen
| ReqBufferEmpty
| ReqBufferUnknown
| ReqBadTableId
| ReqIsSlave
| ReqBadPort
| ReqBadPacket
| ReqMultipartBufOverflow
val badRequest_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> badRequest
val sexp_of_badRequest : badRequest ‑> Ppx_sexp_conv_lib.Sexp.t
type badAction = Frenetic_kernel__OpenFlow0x04.badAction =
| ActBadType
| ActBadLen
| ActBadExp
| ActBadExpType
| ActBadOutPort
| ActBadArg
| ActPermError
| ActTooMany
| ActBadQueue
| ActBadOutGroup
| ActMatchInconsistent
| ActUnsupportedOrder
| ActBadTag
| ActBadSetTyp
| ActBadSetLen
| ActBadSetArg
val badAction_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> badAction
val sexp_of_badAction : badAction ‑> Ppx_sexp_conv_lib.Sexp.t
type badInstruction = Frenetic_kernel__OpenFlow0x04.badInstruction =
| InstUnknownInst
| InstBadTableId
| InstUnsupInst
| InstUnsupMeta
| InstUnsupMetaMask
| InstBadExp
| InstBadExpTyp
| InstBadLen
| InstPermError
val badInstruction_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> badInstruction
val sexp_of_badInstruction : badInstruction ‑> Ppx_sexp_conv_lib.Sexp.t
type badMatch = Frenetic_kernel__OpenFlow0x04.badMatch =
| MatBadTyp
| MatBadLen
| MatBadTag
| MatBadDlAddrMask
| MatBadNwAddrMask
| MatBadWildcards
| MatBadField
| MatBadValue
| MatBadMask
| MatBadPrereq
| MatDupField
| MatPermError
val badMatch_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> badMatch
val sexp_of_badMatch : badMatch ‑> Ppx_sexp_conv_lib.Sexp.t
type flowModFailed = Frenetic_kernel__OpenFlow0x04.flowModFailed =
| FlUnknown
| FlTableFull
| FlBadTableId
| FlOverlap
| FlPermError
| FlBadTimeout
| FlBadCommand
| FlBadFlags
val flowModFailed_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> flowModFailed
val sexp_of_flowModFailed : flowModFailed ‑> Ppx_sexp_conv_lib.Sexp.t
type groupModFailed = Frenetic_kernel__OpenFlow0x04.groupModFailed =
| GrGroupExists
| GrInvalidGroup
| GrWeightUnsupported
| GrOutOfGroups
| GrOutOfBuckets
| GrChainingUnsupported
| GrWatchUnsupported
| GrLoop
| GrUnknownGroup
| GrChainedGroup
| GrBadTyp
| GrBadCommand
| GrBadBucket
| GrBadWatch
| GrPermError
val groupModFailed_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> groupModFailed
val sexp_of_groupModFailed : groupModFailed ‑> Ppx_sexp_conv_lib.Sexp.t
type portModFailed = Frenetic_kernel__OpenFlow0x04.portModFailed =
| PoBadPort
| PoBadHwAddr
| PoBadConfig
| PoBadAdvertise
| PoPermError
val portModFailed_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> portModFailed
val sexp_of_portModFailed : portModFailed ‑> Ppx_sexp_conv_lib.Sexp.t
type tableModFailed = Frenetic_kernel__OpenFlow0x04.tableModFailed =
| TaBadTable
| TaBadConfig
| TaPermError
val tableModFailed_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> tableModFailed
val sexp_of_tableModFailed : tableModFailed ‑> Ppx_sexp_conv_lib.Sexp.t
type queueOpFailed = Frenetic_kernel__OpenFlow0x04.queueOpFailed =
| QuBadPort
| QuBadQueue
| QuPermError
val queueOpFailed_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> queueOpFailed
val sexp_of_queueOpFailed : queueOpFailed ‑> Ppx_sexp_conv_lib.Sexp.t
type switchConfigFailed = Frenetic_kernel__OpenFlow0x04.switchConfigFailed =
| ScBadFlags
| ScBadLen
| ScPermError
val switchConfigFailed_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> switchConfigFailed
val sexp_of_switchConfigFailed : switchConfigFailed ‑> Ppx_sexp_conv_lib.Sexp.t
type roleReqFailed = Frenetic_kernel__OpenFlow0x04.roleReqFailed =
| RoStale
| RoUnsup
| RoBadRole
val roleReqFailed_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> roleReqFailed
val sexp_of_roleReqFailed : roleReqFailed ‑> Ppx_sexp_conv_lib.Sexp.t
type meterModFailed = Frenetic_kernel__OpenFlow0x04.meterModFailed =
| MeUnknown
| MeMeterExists
| MeInvalidMeter
| MeUnknownMeter
| MeBadCommand
| MeBadFlags
| MeBadRate
| MeBadBurst
| MeBadBand
| MeBadBandValue
| MeOutOfMeters
| MeOutOfBands
val meterModFailed_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> meterModFailed
val sexp_of_meterModFailed : meterModFailed ‑> Ppx_sexp_conv_lib.Sexp.t
type tableFeatFailed = Frenetic_kernel__OpenFlow0x04.tableFeatFailed =
| TfBadTable
| TfBadMeta
| TfBadType
| TfBadLen
| TfBadArg
| TfPermError
val tableFeatFailed_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> tableFeatFailed
val sexp_of_tableFeatFailed : tableFeatFailed ‑> Ppx_sexp_conv_lib.Sexp.t
type experimenterFailed = Frenetic_kernel__OpenFlow0x04.experimenterFailed = {
exp_typ : Frenetic_kernel.Packet.int16;
exp_id : int32;
}
val experimenterFailed_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> experimenterFailed
val sexp_of_experimenterFailed : experimenterFailed ‑> Ppx_sexp_conv_lib.Sexp.t
type errorTyp = Frenetic_kernel__OpenFlow0x04.errorTyp =
| HelloFailed of helloFailed
| BadRequest of badRequest
| BadAction of badAction
| BadInstruction of badInstruction
| BadMatch of badMatch
| FlowModFailed of flowModFailed
| GroupModFailed of groupModFailed
| PortModFailed of portModFailed
| TableModFailed of tableModFailed
| QueueOpFailed of queueOpFailed
| SwitchConfigFailed of switchConfigFailed
| RoleReqFailed of roleReqFailed
| MeterModFailed of meterModFailed
| TableFeatFailed of tableFeatFailed
| ExperimenterFailed of experimenterFailed
val errorTyp_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> errorTyp
val sexp_of_errorTyp : errorTyp ‑> Ppx_sexp_conv_lib.Sexp.t
type length = Frenetic_kernel.Packet.int16
val length_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> length
val sexp_of_length : length ‑> Ppx_sexp_conv_lib.Sexp.t
type oxmIPv6ExtHdr = Frenetic_kernel__OpenFlow0x04.oxmIPv6ExtHdr = {
noext : bool;
esp : bool;
auth : bool;
dest : bool;
frac : bool;
router : bool;
hop : bool;
unrep : bool;
unseq : bool;
}
val oxmIPv6ExtHdr_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> oxmIPv6ExtHdr
val sexp_of_oxmIPv6ExtHdr : oxmIPv6ExtHdr ‑> Ppx_sexp_conv_lib.Sexp.t
type oxm = Frenetic_kernel__OpenFlow0x04.oxm =
| OxmInPort of portId
| OxmInPhyPort of portId
| OxmMetadata of int64 mask
| OxmEthType of Frenetic_kernel.Packet.int16
| OxmEthDst of Frenetic_kernel.Packet.int48 mask
| OxmEthSrc of Frenetic_kernel.Packet.int48 mask
| OxmVlanVId of int12 mask
| OxmVlanPcp of Frenetic_kernel.Packet.int8
| OxmIPProto of Frenetic_kernel.Packet.int8
| OxmIPDscp of Frenetic_kernel.Packet.int8
| OxmIPEcn of Frenetic_kernel.Packet.int8
| OxmIP4Src of int32 mask
| OxmIP4Dst of int32 mask
| OxmTCPSrc of Frenetic_kernel.Packet.int16
| OxmTCPDst of Frenetic_kernel.Packet.int16
| OxmARPOp of Frenetic_kernel.Packet.int16
| OxmARPSpa of int32 mask
| OxmARPTpa of int32 mask
| OxmARPSha of Frenetic_kernel.Packet.int48 mask
| OxmARPTha of Frenetic_kernel.Packet.int48 mask
| OxmICMPType of Frenetic_kernel.Packet.int8
| OxmICMPCode of Frenetic_kernel.Packet.int8
| OxmMPLSLabel of int32
| OxmMPLSTc of Frenetic_kernel.Packet.int8
| OxmTunnelId of int64 mask
| OxmUDPSrc of Frenetic_kernel.Packet.int16
| OxmUDPDst of Frenetic_kernel.Packet.int16
| OxmSCTPSrc of Frenetic_kernel.Packet.int16
| OxmSCTPDst of Frenetic_kernel.Packet.int16
| OxmIPv6Src of int128 mask
| OxmIPv6Dst of int128 mask
| OxmIPv6FLabel of int32 mask
| OxmICMPv6Type of Frenetic_kernel.Packet.int8
| OxmICMPv6Code of Frenetic_kernel.Packet.int8
| OxmIPv6NDTarget of int128 mask
| OxmIPv6NDSll of Frenetic_kernel.Packet.int48
| OxmIPv6NDTll of Frenetic_kernel.Packet.int48
| OxmMPLSBos of bool
| OxmPBBIsid of int24 mask
| OxmIPv6ExtHdr of oxmIPv6ExtHdr mask
val oxm_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> oxm
val sexp_of_oxm : oxm ‑> Ppx_sexp_conv_lib.Sexp.t
type oxmMatch = oxm list
val oxmMatch_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> oxmMatch
val sexp_of_oxmMatch : oxmMatch ‑> Ppx_sexp_conv_lib.Sexp.t
val parse_payload : payload ‑> Frenetic_kernel.Packet.packet
val marshal_payload : int32 option ‑> Frenetic_kernel.Packet.packet ‑> payload
val match_all : oxmMatch
type pseudoPort = Frenetic_kernel__OpenFlow0x04.pseudoPort =
| PhysicalPort of portId
| InPort
| Table
| Normal
| Flood
| AllPorts
| Controller of Frenetic_kernel.Packet.int16
| Local
| Any
val pseudoPort_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> pseudoPort
val sexp_of_pseudoPort : pseudoPort ‑> Ppx_sexp_conv_lib.Sexp.t
type actionHdr = Frenetic_kernel__OpenFlow0x04.actionHdr =
| OutputHdr
| GroupHdr
| PopVlanHdr
| PushVlanHdr
| PopMplsHdr
| PushMplsHdr
| SetFieldHdr
| CopyTtlOutHdr
| CopyTtlInHdr
| SetNwTtlHdr
| DecNwTtlHdr
| PushPbbHdr
| PopPbbHdr
| SetMplsTtlHdr
| DecMplsTtlHdr
| SetQueueHdr
| ExperimenterAHdr of int32
val actionHdr_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> actionHdr
val sexp_of_actionHdr : actionHdr ‑> Ppx_sexp_conv_lib.Sexp.t
type action = Frenetic_kernel__OpenFlow0x04.action =
| Output of pseudoPort
| Group of groupId
| PopVlan
| PushVlan of Frenetic_kernel.Packet.int16
| PopMpls of Frenetic_kernel.Packet.int16
| PushMpls of Frenetic_kernel.Packet.int16
| SetField of oxm
| CopyTtlOut
| CopyTtlIn
| SetNwTtl of Frenetic_kernel.Packet.int8
| DecNwTtl
| PushPbb of Frenetic_kernel.Packet.int16
| PopPbb
| SetMplsTtl of Frenetic_kernel.Packet.int8
| DecMplsTtl
| SetQueue of int32
| Experimenter of int32
val action_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> action
val sexp_of_action : action ‑> Ppx_sexp_conv_lib.Sexp.t
type actionSequence = action list
val actionSequence_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> actionSequence
val sexp_of_actionSequence : actionSequence ‑> Ppx_sexp_conv_lib.Sexp.t
type instructionHdr = Frenetic_kernel__OpenFlow0x04.instructionHdr =
| GotoTableHdr
| ApplyActionsHdr
| WriteActionsHdr
| WriteMetadataHdr
| ClearHdr
| MeterHdr
| ExperimenterHdr of int32
val instructionHdr_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> instructionHdr
val sexp_of_instructionHdr : instructionHdr ‑> Ppx_sexp_conv_lib.Sexp.t
type instruction = Frenetic_kernel__OpenFlow0x04.instruction =
| GotoTable of tableId
| ApplyActions of actionSequence
| WriteActions of actionSequence
| WriteMetadata of int64 mask
| Clear
| Meter of int32
| Experimenter of int32
val instruction_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> instruction
val sexp_of_instruction : instruction ‑> Ppx_sexp_conv_lib.Sexp.t
type bucket = Frenetic_kernel__OpenFlow0x04.bucket = {
bu_weight : Frenetic_kernel.Packet.int16;
bu_watch_port : portId option;
bu_watch_group : groupId option;
bu_actions : actionSequence;
}
val bucket_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> bucket
val sexp_of_bucket : bucket ‑> Ppx_sexp_conv_lib.Sexp.t
type groupType = Frenetic_kernel__OpenFlow0x04.groupType =
| All
| Select
| Indirect
| FF
val groupType_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> groupType
val sexp_of_groupType : groupType ‑> Ppx_sexp_conv_lib.Sexp.t
type groupMod = Frenetic_kernel__OpenFlow0x04.groupMod =
| AddGroup of groupType * groupId * bucket list
| DeleteGroup of groupType * groupId
| ModifyGroup of groupType * groupId * bucket list
val groupMod_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> groupMod
val sexp_of_groupMod : groupMod ‑> Ppx_sexp_conv_lib.Sexp.t
type timeout = Frenetic_kernel__OpenFlow0x04.timeout =
| Permanent
| ExpiresAfter of Frenetic_kernel.Packet.int16
val timeout_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> timeout
val sexp_of_timeout : timeout ‑> Ppx_sexp_conv_lib.Sexp.t
type flowModCommand = Frenetic_kernel__OpenFlow0x04.flowModCommand =
| AddFlow
| ModFlow
| ModStrictFlow
| DeleteFlow
| DeleteStrictFlow
val flowModCommand_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> flowModCommand
val sexp_of_flowModCommand : flowModCommand ‑> Ppx_sexp_conv_lib.Sexp.t
type flowModFlags = Frenetic_kernel__OpenFlow0x04.flowModFlags = {
fmf_send_flow_rem : bool;
fmf_check_overlap : bool;
fmf_reset_counts : bool;
fmf_no_pkt_counts : bool;
fmf_no_byt_counts : bool;
}
val flowModFlags_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> flowModFlags
val sexp_of_flowModFlags : flowModFlags ‑> Ppx_sexp_conv_lib.Sexp.t
type flowMod = Frenetic_kernel__OpenFlow0x04.flowMod = {
mfCookie : int64 mask;
mfTable_id : tableId;
mfCommand : flowModCommand;
mfIdle_timeout : timeout;
mfHard_timeout : timeout;
mfPriority : Frenetic_kernel.Packet.int16;
mfBuffer_id : bufferId option;
mfOut_port : pseudoPort option;
mfOut_group : groupId option;
mfFlags : flowModFlags;
mfOfp_match : oxmMatch;
mfInstructions : instruction list;
}
val flowMod_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> flowMod
val sexp_of_flowMod : flowMod ‑> Ppx_sexp_conv_lib.Sexp.t
val add_flow : tbl:tableId ‑> prio:Frenetic_kernel.Packet.int16 ‑> pat:oxmMatch ‑> insts:instruction list ‑> flowMod
val delete_all_flows : flowMod
val delete_all_groups : groupMod
type packetInReason = Frenetic_kernel__OpenFlow0x04.packetInReason =
| NoMatch
| ExplicitSend
| InvalidTTL
val packetInReason_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> packetInReason
val sexp_of_packetInReason : packetInReason ‑> Ppx_sexp_conv_lib.Sexp.t
type packetIn = Frenetic_kernel__OpenFlow0x04.packetIn = {
pi_total_len : Frenetic_kernel.Packet.int16;
pi_reason : packetInReason;
pi_table_id : tableId;
pi_ofp_match : oxmMatch;
pi_payload : payload;
}
val packetIn_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> packetIn
val sexp_of_packetIn : packetIn ‑> Ppx_sexp_conv_lib.Sexp.t
type flowReason = Frenetic_kernel__OpenFlow0x04.flowReason =
| FlowIdleTimeout
| FlowHardTiemout
| FlowDelete
| FlowGroupDelete
val flowReason_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> flowReason
val sexp_of_flowReason : flowReason ‑> Ppx_sexp_conv_lib.Sexp.t
type flowRemoved = Frenetic_kernel__OpenFlow0x04.flowRemoved = {
cookie : int64;
priority : Frenetic_kernel.Packet.int16;
reason : flowReason;
table_id : tableId;
duration_sec : int32;
duration_nsec : int32;
idle_timeout : timeout;
hard_timeout : timeout;
packet_count : int64;
byte_count : int64;
oxm : oxmMatch;
}
val flowRemoved_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> flowRemoved
val sexp_of_flowRemoved : flowRemoved ‑> Ppx_sexp_conv_lib.Sexp.t
type capabilities = Frenetic_kernel__OpenFlow0x04.capabilities = {
flow_stats : bool;
table_stats : bool;
port_stats : bool;
group_stats : bool;
ip_reasm : bool;
queue_stats : bool;
port_blocked : bool;
}
val capabilities_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> capabilities
val sexp_of_capabilities : capabilities ‑> Ppx_sexp_conv_lib.Sexp.t
type portState = Frenetic_kernel__OpenFlow0x04.portState = {
blocked : bool;
live : bool;
}
val portState_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> portState
val sexp_of_portState : portState ‑> Ppx_sexp_conv_lib.Sexp.t
type portConfig = Frenetic_kernel__OpenFlow0x04.portConfig = {
port_down : bool;
no_recv : bool;
no_fwd : bool;
no_packet_in : bool;
}
val portConfig_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> portConfig
val sexp_of_portConfig : portConfig ‑> Ppx_sexp_conv_lib.Sexp.t
type portFeatures = Frenetic_kernel__OpenFlow0x04.portFeatures = {
rate_10mb_hd : bool;
rate_10mb_fd : bool;
rate_100mb_hd : bool;
rate_100mb_fd : bool;
rate_1gb_hd : bool;
rate_1gb_fd : bool;
rate_10gb_fd : bool;
rate_40gb_fd : bool;
rate_100gb_fd : bool;
rate_1tb_fd : bool;
other : bool;
copper : bool;
fiber : bool;
autoneg : bool;
pause : bool;
pause_asym : bool;
}
val portFeatures_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> portFeatures
val sexp_of_portFeatures : portFeatures ‑> Ppx_sexp_conv_lib.Sexp.t
type portDesc = Frenetic_kernel__OpenFlow0x04.portDesc = {
port_no : portId;
hw_addr : Frenetic_kernel.Packet.int48;
name : string;
config : portConfig;
state : portState;
curr : portFeatures;
advertised : portFeatures;
supported : portFeatures;
peer : portFeatures;
curr_speed : int32;
max_speed : int32;
}
val portDesc_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> portDesc
val sexp_of_portDesc : portDesc ‑> Ppx_sexp_conv_lib.Sexp.t
type portMod = Frenetic_kernel__OpenFlow0x04.portMod = {
mpPortNo : portId;
mpHw_addr : Frenetic_kernel.Packet.int48;
mpConfig : portConfig;
mpMask : int32;
mpAdvertise : portFeatures;
}
val portMod_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> portMod
val sexp_of_portMod : portMod ‑> Ppx_sexp_conv_lib.Sexp.t
type portReason = Frenetic_kernel__OpenFlow0x04.portReason =
| PortAdd
| PortDelete
| PortModify
val portReason_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> portReason
val sexp_of_portReason : portReason ‑> Ppx_sexp_conv_lib.Sexp.t
type portStatus = Frenetic_kernel__OpenFlow0x04.portStatus = {
reason : portReason;
desc : portDesc;
}
val portStatus_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> portStatus
val sexp_of_portStatus : portStatus ‑> Ppx_sexp_conv_lib.Sexp.t
type packetOut = Frenetic_kernel__OpenFlow0x04.packetOut = {
po_payload : payload;
po_port_id : portId option;
po_actions : actionSequence;
}
val packetOut_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> packetOut
val sexp_of_packetOut : packetOut ‑> Ppx_sexp_conv_lib.Sexp.t
type rate = int32
val rate_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> rate
val sexp_of_rate : rate ‑> Ppx_sexp_conv_lib.Sexp.t
type burst = int32
val burst_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> burst
val sexp_of_burst : burst ‑> Ppx_sexp_conv_lib.Sexp.t
type experimenterId = int32
val experimenterId_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> experimenterId
val sexp_of_experimenterId : experimenterId ‑> Ppx_sexp_conv_lib.Sexp.t
type meterBand = Frenetic_kernel__OpenFlow0x04.meterBand =
| Drop of rate * burst
| DscpRemark of rate * burst * Frenetic_kernel.Packet.int8
| ExpMeter of rate * burst * experimenterId
val meterBand_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> meterBand
val sexp_of_meterBand : meterBand ‑> Ppx_sexp_conv_lib.Sexp.t
type meterCommand = Frenetic_kernel__OpenFlow0x04.meterCommand =
| AddMeter
| ModifyMeter
| DeleteMeter
val meterCommand_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> meterCommand
val sexp_of_meterCommand : meterCommand ‑> Ppx_sexp_conv_lib.Sexp.t
type meterFlags = Frenetic_kernel__OpenFlow0x04.meterFlags = {
kbps : bool;
pktps : bool;
burst : bool;
stats : bool;
}
val meterFlags_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> meterFlags
val sexp_of_meterFlags : meterFlags ‑> Ppx_sexp_conv_lib.Sexp.t
type meterMod = Frenetic_kernel__OpenFlow0x04.meterMod = {
command : meterCommand;
flags : meterFlags;
meter_id : int32;
bands : meterBand list;
}
val meterMod_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> meterMod
val sexp_of_meterMod : meterMod ‑> Ppx_sexp_conv_lib.Sexp.t
type flowRequest = Frenetic_kernel__OpenFlow0x04.flowRequest = {
fr_table_id : tableId;
fr_out_port : portId;
fr_out_group : portId;
fr_match : oxmMatch;
}
val flowRequest_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> flowRequest
val sexp_of_flowRequest : flowRequest ‑> Ppx_sexp_conv_lib.Sexp.t
type queueRequest = Frenetic_kernel__OpenFlow0x04.queueRequest = {
port_number : portId;
queue_id : int32;
}
val queueRequest_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> queueRequest
val sexp_of_queueRequest : queueRequest ‑> Ppx_sexp_conv_lib.Sexp.t
type experimenter = Frenetic_kernel__OpenFlow0x04.experimenter = {
exp_id : experimenterId;
exp_type : int32;
}
val experimenter_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> experimenter
val sexp_of_experimenter : experimenter ‑> Ppx_sexp_conv_lib.Sexp.t
type tableFeatureProp = Frenetic_kernel__OpenFlow0x04.tableFeatureProp =
| TfpInstruction of instructionHdr list
| TfpInstructionMiss of instructionHdr list
| TfpNextTable of tableId list
| TfpNextTableMiss of tableId list
| TfpWriteAction of actionHdr list
| TfpWriteActionMiss of actionHdr list
| TfpApplyAction of actionHdr list
| TfpApplyActionMiss of actionHdr list
| TfpMatch of oxm list
| TfpWildcard of oxm list
| TfpWriteSetField of oxm list
| TfpWriteSetFieldMiss of oxm list
| TfpApplySetField of oxm list
| TfpApplySetFieldMiss of oxm list
| TfpExperimenter of experimenter * Cstruct.t
| TfpExperimenterMiss of experimenter * Cstruct.t
val tableFeatureProp_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> tableFeatureProp
val sexp_of_tableFeatureProp : tableFeatureProp ‑> Ppx_sexp_conv_lib.Sexp.t
type tableConfig = Frenetic_kernel__OpenFlow0x04.tableConfig =
| Deprecated
val tableConfig_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> tableConfig
val sexp_of_tableConfig : tableConfig ‑> Ppx_sexp_conv_lib.Sexp.t
type tableFeatures = Frenetic_kernel__OpenFlow0x04.tableFeatures = {
length : Frenetic_kernel.Packet.int16;
table_id : tableId;
name : string;
metadata_match : int64;
metadata_write : int64;
config : tableConfig;
max_entries : int32;
feature_prop : tableFeatureProp list;
}
val tableFeatures_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> tableFeatures
val sexp_of_tableFeatures : tableFeatures ‑> Ppx_sexp_conv_lib.Sexp.t
type multipartType = Frenetic_kernel__OpenFlow0x04.multipartType =
| SwitchDescReq
| PortsDescReq
| FlowStatsReq of flowRequest
| AggregFlowStatsReq of flowRequest
| TableStatsReq
| PortStatsReq of portId
| QueueStatsReq of queueRequest
| GroupStatsReq of int32
| GroupDescReq
| GroupFeatReq
| MeterStatsReq of int32
| MeterConfReq of int32
| MeterFeatReq
| TableFeatReq of tableFeatures list option
| ExperimentReq of experimenter
val multipartType_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> multipartType
val sexp_of_multipartType : multipartType ‑> Ppx_sexp_conv_lib.Sexp.t
type multipartRequest = Frenetic_kernel__OpenFlow0x04.multipartRequest = {
mpr_type : multipartType;
mpr_flags : bool;
}
val multipartRequest_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> multipartRequest
val sexp_of_multipartRequest : multipartRequest ‑> Ppx_sexp_conv_lib.Sexp.t
val portDescReq : multipartRequest
type switchDesc = Frenetic_kernel__OpenFlow0x04.switchDesc = {
mfr_desc : string;
hw_desc : string;
sw_desc : string;
serial_num : string;
dp_desc : string;
}
val switchDesc_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> switchDesc
val sexp_of_switchDesc : switchDesc ‑> Ppx_sexp_conv_lib.Sexp.t
type flowStats = Frenetic_kernel__OpenFlow0x04.flowStats = {
table_id : tableId;
duration_sec : int32;
duration_nsec : int32;
priority : Frenetic_kernel.Packet.int16;
idle_timeout : timeout;
hard_timeout : timeout;
flags : flowModFlags;
cookie : int64;
packet_count : int64;
byte_count : int64;
ofp_match : oxmMatch;
instructions : instruction list;
}
val flowStats_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> flowStats
val sexp_of_flowStats : flowStats ‑> Ppx_sexp_conv_lib.Sexp.t
type aggregStats = Frenetic_kernel__OpenFlow0x04.aggregStats = {
packet_count : int64;
byte_count : int64;
flow_count : int32;
}
val aggregStats_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> aggregStats
val sexp_of_aggregStats : aggregStats ‑> Ppx_sexp_conv_lib.Sexp.t
type tableStats = Frenetic_kernel__OpenFlow0x04.tableStats = {
table_id : tableId;
active_count : int32;
lookup_count : int64;
matched_count : int64;
}
val tableStats_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> tableStats
val sexp_of_tableStats : tableStats ‑> Ppx_sexp_conv_lib.Sexp.t
type portStats = Frenetic_kernel__OpenFlow0x04.portStats = {
psPort_no : portId;
rx_packets : int64;
tx_packets : int64;
rx_bytes : int64;
tx_bytes : int64;
rx_dropped : int64;
tx_dropped : int64;
rx_errors : int64;
tx_errors : int64;
rx_frame_err : int64;
rx_over_err : int64;
rx_crc_err : int64;
collisions : int64;
duration_sec : int32;
duration_nsec : int32;
}
val portStats_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> portStats
val sexp_of_portStats : portStats ‑> Ppx_sexp_conv_lib.Sexp.t
type queueStats = Frenetic_kernel__OpenFlow0x04.queueStats = {
qsPort_no : portId;
queue_id : int32;
tx_bytes : int64;
tx_packets : int64;
tx_errors : int64;
duration_sec : int32;
duration_nsec : int32;
}
val queueStats_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> queueStats
val sexp_of_queueStats : queueStats ‑> Ppx_sexp_conv_lib.Sexp.t
type bucketStats = Frenetic_kernel__OpenFlow0x04.bucketStats = {
packet_count : int64;
byte_count : int64;
}
val bucketStats_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> bucketStats
val sexp_of_bucketStats : bucketStats ‑> Ppx_sexp_conv_lib.Sexp.t
type groupStats = Frenetic_kernel__OpenFlow0x04.groupStats = {
length : Frenetic_kernel.Packet.int16;
group_id : int32;
ref_count : int32;
packet_count : int64;
byte_count : int64;
duration_sec : int32;
duration_nsec : int32;
bucket_stats : bucketStats list;
}
val groupStats_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> groupStats
val sexp_of_groupStats : groupStats ‑> Ppx_sexp_conv_lib.Sexp.t
type groupDesc = Frenetic_kernel__OpenFlow0x04.groupDesc = {
length : Frenetic_kernel.Packet.int16;
typ : groupType;
group_id : int32;
bucket : bucket list;
}
val groupDesc_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> groupDesc
val sexp_of_groupDesc : groupDesc ‑> Ppx_sexp_conv_lib.Sexp.t
type groupCapabilities = Frenetic_kernel__OpenFlow0x04.groupCapabilities = {
select_weight : bool;
select_liveness : bool;
chaining : bool;
chaining_checks : bool;
}
val groupCapabilities_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> groupCapabilities
val sexp_of_groupCapabilities : groupCapabilities ‑> Ppx_sexp_conv_lib.Sexp.t
type groupTypeMap = Frenetic_kernel__OpenFlow0x04.groupTypeMap = {
all : bool;
select : bool;
indirect : bool;
ff : bool;
}
val groupTypeMap_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> groupTypeMap
val sexp_of_groupTypeMap : groupTypeMap ‑> Ppx_sexp_conv_lib.Sexp.t
type actionTypeMap = Frenetic_kernel__OpenFlow0x04.actionTypeMap = {
output : bool;
copy_ttl_out : bool;
copy_ttl_in : bool;
set_mpls_ttl : bool;
dec_mpls_ttl : bool;
push_vlan : bool;
pop_vlan : bool;
push_mpls : bool;
pop_mpls : bool;
set_queue : bool;
group : bool;
set_nw_ttl : bool;
dec_nw_ttl : bool;
set_field : bool;
push_pbb : bool;
pop_pbb : bool;
}
val actionTypeMap_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> actionTypeMap
val sexp_of_actionTypeMap : actionTypeMap ‑> Ppx_sexp_conv_lib.Sexp.t
type groupFeatures = Frenetic_kernel__OpenFlow0x04.groupFeatures = {
typ : groupTypeMap;
capabilities : groupCapabilities;
max_groups_all : int32;
max_groups_select : int32;
max_groups_indirect : int32;
max_groups_ff : int32;
actions_all : actionTypeMap;
actions_select : actionTypeMap;
actions_indirect : actionTypeMap;
actions_ff : actionTypeMap;
}
val groupFeatures_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> groupFeatures
val sexp_of_groupFeatures : groupFeatures ‑> Ppx_sexp_conv_lib.Sexp.t
type meterBandStats = Frenetic_kernel__OpenFlow0x04.meterBandStats = {
packet_band_count : int64;
byte_band_count : int64;
}
val meterBandStats_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> meterBandStats
val sexp_of_meterBandStats : meterBandStats ‑> Ppx_sexp_conv_lib.Sexp.t
type meterStats = Frenetic_kernel__OpenFlow0x04.meterStats = {
meter_id : int32;
len : Frenetic_kernel.Packet.int16;
flow_count : int32;
packet_in_count : int64;
byte_in_count : int64;
duration_sec : int32;
duration_nsec : int32;
band : meterBandStats list;
}
val meterStats_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> meterStats
val sexp_of_meterStats : meterStats ‑> Ppx_sexp_conv_lib.Sexp.t
type meterConfig = Frenetic_kernel__OpenFlow0x04.meterConfig = {
length : length;
flags : meterFlags;
meter_id : int32;
bands : meterBand list;
}
val meterConfig_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> meterConfig
val sexp_of_meterConfig : meterConfig ‑> Ppx_sexp_conv_lib.Sexp.t
type meterBandMaps = Frenetic_kernel__OpenFlow0x04.meterBandMaps = {
drop : bool;
dscpRemark : bool;
}
val meterBandMaps_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> meterBandMaps
val sexp_of_meterBandMaps : meterBandMaps ‑> Ppx_sexp_conv_lib.Sexp.t
type meterFeatures = Frenetic_kernel__OpenFlow0x04.meterFeatures = {
max_meter : int32;
band_typ : meterBandMaps;
capabilities : meterFlags;
max_band : Frenetic_kernel.Packet.int8;
max_color : Frenetic_kernel.Packet.int8;
}
val meterFeatures_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> meterFeatures
val sexp_of_meterFeatures : meterFeatures ‑> Ppx_sexp_conv_lib.Sexp.t
type multipartReplyTyp = Frenetic_kernel__OpenFlow0x04.multipartReplyTyp =
| PortsDescReply of portDesc list
| SwitchDescReply of switchDesc
| FlowStatsReply of flowStats list
| AggregateReply of aggregStats
| TableReply of tableStats list
| TableFeaturesReply of tableFeatures list
| PortStatsReply of portStats list
| QueueStatsReply of queueStats list
| GroupStatsReply of groupStats list
| GroupDescReply of groupDesc list
| GroupFeaturesReply of groupFeatures
| MeterReply of meterStats list
| MeterConfig of meterConfig list
| MeterFeaturesReply of meterFeatures
val multipartReplyTyp_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> multipartReplyTyp
val sexp_of_multipartReplyTyp : multipartReplyTyp ‑> Ppx_sexp_conv_lib.Sexp.t
type multipartReply = Frenetic_kernel__OpenFlow0x04.multipartReply = {
mpreply_typ : multipartReplyTyp;
mpreply_flags : bool;
}
val multipartReply_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> multipartReply
val sexp_of_multipartReply : multipartReply ‑> Ppx_sexp_conv_lib.Sexp.t
type tableMod = Frenetic_kernel__OpenFlow0x04.tableMod = {
table_id : tableId;
config : tableConfig;
}
val tableMod_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> tableMod
val sexp_of_tableMod : tableMod ‑> Ppx_sexp_conv_lib.Sexp.t
type rateQueue = Frenetic_kernel__OpenFlow0x04.rateQueue =
| Rate of int
| Disabled
val rateQueue_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> rateQueue
val sexp_of_rateQueue : rateQueue ‑> Ppx_sexp_conv_lib.Sexp.t
type queueProp = Frenetic_kernel__OpenFlow0x04.queueProp =
| MinRateProp of rateQueue
| MaxRateProp of rateQueue
| ExperimenterProp of int32
val queueProp_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> queueProp
val sexp_of_queueProp : queueProp ‑> Ppx_sexp_conv_lib.Sexp.t
type queueDesc = Frenetic_kernel__OpenFlow0x04.queueDesc = {
queue_id : int32;
port : portId;
len : Frenetic_kernel.Packet.int16;
properties : queueProp list;
}
val queueDesc_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> queueDesc
val sexp_of_queueDesc : queueDesc ‑> Ppx_sexp_conv_lib.Sexp.t
type queueConfReq = Frenetic_kernel__OpenFlow0x04.queueConfReq = {
port : portId;
}
val queueConfReq_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> queueConfReq
val sexp_of_queueConfReq : queueConfReq ‑> Ppx_sexp_conv_lib.Sexp.t
type queueConfReply = Frenetic_kernel__OpenFlow0x04.queueConfReply = {
port : portId;
queues : queueDesc list;
}
val queueConfReply_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> queueConfReply
val sexp_of_queueConfReply : queueConfReply ‑> Ppx_sexp_conv_lib.Sexp.t
type controllerRole = Frenetic_kernel__OpenFlow0x04.controllerRole =
| NoChangeRole
| EqualRole
| MasterRole
| SlaveRole
val controllerRole_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> controllerRole
val sexp_of_controllerRole : controllerRole ‑> Ppx_sexp_conv_lib.Sexp.t
type roleRequest = Frenetic_kernel__OpenFlow0x04.roleRequest = {
role : controllerRole;
generation_id : int64;
}
val roleRequest_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> roleRequest
val sexp_of_roleRequest : roleRequest ‑> Ppx_sexp_conv_lib.Sexp.t
type supportedList = int list
val supportedList_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> supportedList
val sexp_of_supportedList : supportedList ‑> Ppx_sexp_conv_lib.Sexp.t
type element = Frenetic_kernel__OpenFlow0x04.element =
| VersionBitMap of supportedList
val element_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> element
val sexp_of_element : element ‑> Ppx_sexp_conv_lib.Sexp.t
type helloElement = element list
val helloElement_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> helloElement
val sexp_of_helloElement : helloElement ‑> Ppx_sexp_conv_lib.Sexp.t
type packetInReasonMap = Frenetic_kernel__OpenFlow0x04.packetInReasonMap = {
table_miss : bool;
apply_action : bool;
invalid_ttl : bool;
}
val packetInReasonMap_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> packetInReasonMap
val sexp_of_packetInReasonMap : packetInReasonMap ‑> Ppx_sexp_conv_lib.Sexp.t
type portReasonMap = Frenetic_kernel__OpenFlow0x04.portReasonMap = {
add : bool;
delete : bool;
modify : bool;
}
val portReasonMap_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> portReasonMap
val sexp_of_portReasonMap : portReasonMap ‑> Ppx_sexp_conv_lib.Sexp.t
type flowReasonMask = Frenetic_kernel__OpenFlow0x04.flowReasonMask = {
idle_timeout : bool;
hard_timeout : bool;
delete : bool;
group_delete : bool;
}
val flowReasonMask_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> flowReasonMask
val sexp_of_flowReasonMask : flowReasonMask ‑> Ppx_sexp_conv_lib.Sexp.t
type asyncConfig = Frenetic_kernel__OpenFlow0x04.asyncConfig = {
packet_in : packetInReasonMap asyncMask;
port_status : portReasonMap asyncMask;
flow_removed : flowReasonMask asyncMask;
}
val asyncConfig_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> asyncConfig
val sexp_of_asyncConfig : asyncConfig ‑> Ppx_sexp_conv_lib.Sexp.t
type msg_code = Frenetic_kernel__OpenFlow0x04.msg_code =
| HELLO
| ERROR
| ECHO_REQ
| ECHO_RESP
| VENDOR
| FEATURES_REQ
| FEATURES_RESP
| GET_CONFIG_REQ
| GET_CONFIG_RESP
| SET_CONFIG
| PACKET_IN
| FLOW_REMOVED
| PORT_STATUS
| PACKET_OUT
| FLOW_MOD
| GROUP_MOD
| PORT_MOD
| TABLE_MOD
| MULTIPART_REQ
| MULTIPART_RESP
| BARRIER_REQ
| BARRIER_RESP
| QUEUE_GET_CONFIG_REQ
| QUEUE_GET_CONFIG_RESP
| ROLE_REQ
| ROLE_RESP
| GET_ASYNC_REQ
| GET_ASYNC_REP
| SET_ASYNC
| METER_MOD
val msg_code_to_int : msg_code ‑> int
module PortConfig : sig ... end
module PortFeatures : sig ... end
module Oxm : sig ... end
module PseudoPort : sig ... end
module QueueDesc : sig ... end
module SwitchConfig : sig ... end
module OfpMatch : sig ... end
module Action : sig ... end
module Bucket : sig ... end
module FlowModCommand : sig ... end
module GroupType : sig ... end
module GroupMod : sig ... end
module PortMod : sig ... end
module MeterMod : sig ... end
module Instruction : sig ... end
module Instructions : sig ... end
module FlowMod : sig ... end
module Capabilities : sig ... end
type switchFeatures = Frenetic_kernel__OpenFlow0x04.switchFeatures = {
datapath_id : int64;
num_buffers : int32;
num_tables : Frenetic_kernel.Packet.int8;
aux_id : Frenetic_kernel.Packet.int8;
supported_capabilities : capabilities;
}
module SwitchFeatures : sig ... end
module PortState : sig ... end
module PortDesc : sig ... end
module PortStatus : sig ... end
module PacketIn : sig ... end
module PacketOut : sig ... end
module MeterBand : sig ... end
module FlowRemoved : sig ... end
module FlowRequest : sig ... end
module QueueRequest : sig ... end
module TableFeatureProp : sig ... end
module TableFeature : sig ... end
module MultipartReq : sig ... end
module GroupStats : sig ... end
module SwitchDescriptionReply : sig ... end
module FlowStats : sig ... end
module AggregateStats : sig ... end
module TableStats : sig ... end
module PortStats : sig ... end
module QueueStats : sig ... end
module GroupDesc : sig ... end
module GroupFeatures : sig ... end
module MeterStats : sig ... end
module MeterConfig : sig ... end
module MeterFeatures : sig ... end
module MultipartReply : sig ... end
module TableMod : sig ... end
module QueueConfReq : sig ... end
module QueueConfReply : sig ... end
type error = Frenetic_kernel__OpenFlow0x04.error = {
err : errorTyp;
data : Cstruct.t;
}
module Error : sig ... end
module RoleRequest : sig ... end
module Hello : sig ... end
module AsyncConfig : sig ... end
module Message : sig ... end