Module Frenetic_kernel.OpenFlow.Pattern.Ip

type t = Packet.nwAddr * int32
include sig ... end
val t_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> t
val sexp_of_t : t ‑> Ppx_sexp_conv_lib.Sexp.t
val match_all : t

match_all is pattern that matches any address

val less_eq : t ‑> t ‑> bool

less_eq x1 x2 returns true when x2 matches any address that x1 will match

val eq : t ‑> t ‑> bool

eq p1 p2 returns true when p1 and p2 match the same set of addresses

val join : t ‑> t ‑> t

join p1 p2 is the least pattern pm such that less_eq p1 pm and less_eq p2 pm

val intersect : t ‑> t ‑> t option

intersect x1 x2 returns the intersection of when x1 and x2

val compatible : t ‑> t ‑> bool

compatible x1 x2 returns true when x1 and x2 have a non-empty intersection

val shift : t ‑> int32

ip_shift x returns an int32 after shifting x by its mask

val format : Format.formatter ‑> t ‑> unit
val string_of : t ‑> string