Module Frenetic_kernel.OpenFlow.Pattern

module Ip : sig ... end

type t = {

dlSrc : Packet.dlAddr option;

dlDst : Packet.dlAddr option;

dlTyp : Packet.dlTyp option;

dlVlan : Packet.dlVlan;

dlVlanPcp : Packet.dlVlanPcp option;

nwSrc : Ip.t option;

nwDst : Ip.t option;

nwProto : Packet.nwProto option;

tpSrc : Packet.tpPort option;

tpDst : Packet.tpPort option;

inPort : portId option;

}

WARNING: There are dependencies between different fields that must be met

include sig ... end

val t_of_sexp : Ppx_sexp_conv_lib.Sexp.t ‑> t

val sexp_of_t : t ‑> Ppx_sexp_conv_lib.Sexp.t

val match_all : t

match_all is pattern that matches any packet

val less_eq : t ‑> t ‑> bool

less_eq p1 p2 returns true when p2 matches any packet that p1 will match

val eq : t ‑> t ‑> bool

eq p1 p2 returns true when p1 and p2 match the same set of packets

val join : t ‑> t ‑> t

join p1 p2 is the least pattern pm such that less_eq p1 pm and less_eq p2 pm

val format : Format.formatter ‑> t ‑> unit

val string_of : t ‑> string